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Electrical properties of orientation-mismatched interface of (311)B InP/(100) GaAs, and the effect of surface preparation methods

机译:(311)B INP /(100)GaAs的取向 - 失配界面的电气性能,以及表面制备方法的影响

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We investigated electrical conductivity across orientation- and lattice mismatched interface formed by wafer bonding. An interface of (311)B InP and (100) GaAs wafer had a barrier height (Vb) of about 0.5 eV, which was higher than that of a bonded interface of (100) InP/(100) GaAs due to an orientation mismatch. The effect of surface treatment method before the bonding process was also investigated, and it was shown that the Vb is lower for the interface formed by bonding wafers with dry surface. Although the Vb was high for the (311)B InP/(100) GaAs interface, it had a decent conductivity, and we believe that such an integrated structure is beneficial for fabricating new types of devices such as long-wavelength VCSEL with polarization control.
机译:我们调查了通过晶片键合形成的方向和晶格不匹配界面的导电性。 (311)B INP和(100)GaAs晶片的界面具有约0.5eV的屏障高度(VB),其由于取向不匹配而高于(100)InP /(100)GaAs的键合界面的封端界面 。 还研究了表面处理方法在结合过程之前的影响,结果表明,通过将晶片与干燥表面粘合晶片形成的界面,VB较低。 虽然(311)B INP /(100)GaAs接口的VB很高,但它具有体面的电导率,并且我们认为这种综合结构是有利于制造具有偏振控制的长波长VCSEL的新型设备 。

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