Low-Power All-Digital ΔΣ TDC with Bi-directional Gated Delay Line Time Integrator

摘要

This paper presents a low-power time integrator and its applications in an all-digital first-order ΔΣ time-to-digital converter (TDC). The time integrator is realized using a bi-directional gated delay line (BD-GDL) with time variable to be integrated as the gating signal. The integration of the time variable is obtained via the accumulation of the charge of the load capacitor and the logic state of gated delay stages. Issues affecting the performance of the time integrator and TDC are examined. An all-digital first-order ΔΣ TDC utilizing the time integrator was designed in an IBM 130 nm 1.2 V CMOS technology. A sinusoid time input of 430 ps amplitude and 231 kHz frequency with oversampling ratio 54 was digitized by the modulator. The TDC provides first-order noise-shaping and a SNR of 39.98 dB over the signal band 36 ～ 231 kHz consuming 46 μW.