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A FPGA-Based Feature Extraction using Reconfigurable Rotated Wavelet Transform for Various Classification Schemes

机译:基于FPGA的特征提取,可用于各种分类方案的可重构旋转小波变换

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A novel approach of an embedded FPGA-based design for feature extraction using reconfigurable rotated wavelet transform (RWT) for various classification schemes is proposed. A new set of filter bank coefficients is generated by rotating a standard 1D discrete wavelet filter (DWF) in order to overcome shortcomings inherent in conventional ways of feature extraction such as discrete wavelet transform (DWT). We tested our approach by conducting a fault classification experiment using DWT and RWT for feature extraction. The DWT yields an accurate classification efficiency of 73.33%, while the RWT yields 86.67%. The proposed architecture consists of a datapath module, a controller module and ROM, which contains filter coefficients and input image pixel data. The datapath module performs the feature extraction in four orientations using only four multipliers and adders irrespective of the DWF employed. Despite being slightly more complex to execute, the results of the proposed RWT architecture are comparable with the existing DWT architectures in various aspects such as hardware resources, computational time and power consumption.
机译:提出了一种使用用于各种分类方案的可重构旋转小波变换(RWT)的特征提取的嵌入式FPGA设计的新方法。通过旋转标准的1D离散小波滤波器(DWF)来产生一组新的滤波器组系数,以克服传统的特征提取方式所固有的缺点,例如离散小波变换(DWT)。我们通过使用DWT和RWT进行故障分类实验来测试我们的方法进行特征提取。 DWT的准确分类效率为73.33%,而RWT产量为86.67%。所提出的架构包括DataPath模块,控制器模块和ROM,其中包含滤波器系数和输入图像像素数据。数据路径模块使用四个乘法器和加法器在四个方向上执行特征提取,而不管使用的DWF如何。尽管执行稍微复杂,但所提出的RWT架构的结果与在硬件资源,计算时间和功耗等各个方面的现有DWT架构相当。

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