Transistor Placement Strategies for Non-Series-Parallel Cells

摘要

Regarding optimized logic network generation, recent papers have demonstrated that non-series-parallel topologies can deliver arrangements with fewer transistors when compared to the widely used series-parallel approach. However, due to its topology particularities, this paradigm represents a challenge for physical cell design, especially concerning the transistor placement procedure. In this scenario, we present an analysis of two divergent placement strategies: the first based on a continuous active area approach, aiming to produce cells with minimized diffusion gaps, and the second based on a continuous polysilicon gates paradigm, where the target is to maximize the vertical gates alignment. In order to evaluate both placement policies regarding geometrical and electrical aspects, we performed experiments in a well-known benchmark. The continuous polysilicon gates strategy presented optimizations in the cell area, wirelength, input capacitance, leakage, internal and switching power, while the continuous active area strategy showed better results concerning propagation and transition delay. These results can be used as a guide to an adaptive placement methodology implemented in automatic layout design tools to deal with non-series-parallel arrangements.