Variable length coding (VLC) is a widely used technique in digital video compression systems. It is known for its efficient compression, but is susceptible to noisy environments. Due to the increased demand for multimedia systems to be portable, power consumption and power saving become important issues. Current ITU H.263+ and ISO MPEG-4 standards have used reversible variable length coding (RVLC) which provides greater error robustness than non-reversible counterparts (VLC) due to the growing need for wireless exchange of compressed image and video signals over noisy channels. In this paper, a new method for RVLC decoding is described. Since the special structure of RVLC codewords, the decoding techniques that are common for regular VLC are less efficient when used with RVLC. The new method uses simple logical operations to determine the length of codewords quickly, and then codewords are decoded. It is easily implemented with hardware. We propose a VLSI architecture based on this new method. The architecture also uses the technique of table partitioning. The experimental result shows that our architecture can achieve lower power consumption without sacrificing the quality of the performance. The proposed architecture has been implemented using standard cell methodology for TSMC 0.18um 1P6M technology. The chip implementation results show that proposed architecture can work at 100MHz and its power consumption is only 46.69 uW/MHz.
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