Estimation of inter-symbol interference using clock pattern

摘要

Due to advancement in technology and higher demand of frequency, the effect of jitter components, especially inter-symbol interference (ISI), plays significant impact on performance of high speed serial links. The analysis of jitter components is useful for testing of high speed circuits. In this paper, an efficient methodology for estimation of inter-symbol interference using clock pattern is described and a brief overview of other jitter components segregation techniques are introduced. This methodology is implemented in MATLAB and the results are efficiently verified with other CAD tools such as Agilent ADS and with adaptive filtration method (also known as equalization method). The error percentages in proposed method are within 12%.