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Methods and apparatus for generating short length patterns that induce inter-symbol interference
Methods and apparatus for generating short length patterns that induce inter-symbol interference
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机译:产生引起码间干扰的短码型的方法和装置
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摘要
One embodiment relates to a method of generating worst case inter-symbol interference (ISI) inducing short patterns for simulating and/or testing a communication link. The method includes the generation of a binary clock sequence comprising bits of alternating values at the beginning of the pattern. In addition, an ISI inducing binary sequences and its complement are generated after the clock sequence. Another embodiment relates to a pattern generator for generating an worst case inter-symbol interference inducing short pattern for testing a communication link. Other embodiments, aspects, and features are also disclosed.
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