Gilbert Cell Mixer Design Based on a Novel Systematic Approach for Nanoscale Technologies

摘要

The paper presents a systematic methodology for designing a CMOS down-conversion mixer based on a conventional double balanced Gilbert cell. The design flow exploits the g_m/I_D methodology in order to optimize the size of the transistors that allow achieving the best tradeoff between conversion gain, noise figure, third-order intercept and power DC consumption of the entire system. The mixer was designed using a 0.13 μm process from IHP Microelectronics, and it exhibits a final conversion gain of 10.3 dB @ 0 dBm local oscillator power. The average noise figure is about 12 dB and the input third-order intercept is 0 dBm. Finally, the chip-core without bonding pads measures only 0.028 mm × 0.034 mm and it dissipates 4.4 mW with 1.5 V supply.