A dynamic substructural method (DSM) is developed to simulate the board level drop test of a wafer level chip scale package (WL-CSP). Parametric study on package location at the test board, printed circuit board (PCB) thickness and WL-CSP package thickness is conducted in the board level drop test simulations. The peeling stress and first principle stress of the solder joints are checked and discussed. Simulation results show that dynamic substructure method can obtain the satisfied simulation accuracy while the computing time has significantly decreased. Package at location U1 will fail firstly following by U3 and U8 according to simulation results. The maximum first principal stress and peeling stress at location U1 increase when PCB thickness increases while the maximum first principal stress and peeling stress increases slowly when package thickness increases.
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