Infineon Platform for SoC IO Ring and Package Design

摘要

Infineon Platform for SoC IO Ring and Package Design is a methodology for defining pad/port connectivity, the I/O ring and ball-outs (bumps). Along with the support for wire bond packaging technology, the platform also supports flip chip packaging features such as hard macros/3rd party IPs and n-to-m relationships between pads and bumps. The methodology provides complete automation for I/O fabric and netlist generation in the chip design cycle. This methodology by automatically generating and validating the I/O fabric from single source specification can ease SoC I/O integration significantly, drastically reducing time to market time with an added advantage of eliminating design bugs.