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Ultra-low noise and high PSR LDO design

机译:超低噪声和高PSR LDO设计

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This paper presents a new ultra-low noise and high PSR LDO structure. This structure can achieve ultra-low noise performance without large filter capacitor by incorporating a capacitance amplifying circuit in the structure of LDO with pre-regulation. A large amount of chip area will be saved in this structure. Also this structure can achieve high PSR under a wide frequency range by introducing a feed-forward path between the drain and gate of the pass transistor. A novel LDO in proposed structure is realized under SMIC 0.18µm process. The experimental results show that proposed LDO structure can achieve a total output noise of 25.5µV between 10Hz–1KHz and 56.4µV between 1KHz-1MHz with a filter capacitor of 5pF. PSR is −71.6dB under low frequency until 49KHz and at least −65.7dB under entire frequency range.
机译:本文提出了一种新的超低噪声和高PSR LDO结构。通过在具有预调节功能的LDO结构中加入电容放大电路,该结构无需大型滤波电容器即可实现超低噪声性能。这种结构将节省大量芯片面积。而且,通过在传输晶体管的漏极和栅极之间引入前馈路径,该结构可以在较宽的频率范围内实现较高的PSR。在SMIC 0.18µm工艺下,可以实现所提出结构的新型LDO。实验结果表明,采用5pF的滤波电容器,所提出的LDO结构可在10Hz-1KHz之间实现25.5µV的总输出噪声,而在1KHz-1MHz之间实现56.4µV的总输出噪声。低频直到49KHz为止的PSR为-71.6dB,在整个频率范围内至少为-65.7dB。

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