Design of a Feedback Loop Circuit for Quadrature Error Correction in 90-nm CMOS

摘要

A feedback loop circuit for in-phase/ quadrature error correction is proposed. The design is comprised of XOR/XNOR, duty cycle detector with amplifier and dual controlled variable delay cells. The presented circuit is composed of phase lock loop (PLL) type structure for error correction. The circuit is biased at 1.2 V and consumed 3.768 mA. The circuit corrects phase error up to 3.5% at 500 MHz, 1.48% at 750 MHz, 1.1% at 1GHz, 0.97% at 1.5 GHz and 1.25% at 2.5 GHz.