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Design of CMOS continuous-time multiple-loop feedback filters.

机译:CMOS连续时间多回路反馈滤波器的设计。

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摘要

The subject of this dissertation is a new design approach for integrated {dollar}gsb{lcub}m{rcub}{dollar}-C filters, the inverse-follow-the-leader feedback (IFLF) topology. This new approach is one of the well-known multiple-loop feedback topologies. The magnitude sensitivity to component variations for IFLF filters is known to be better than that for cascade bandpass filters. For modern applications, such as in hard disc drives and wireless communications, the group delay of the filter is important. However, comparative information about the group delay performance between IFLF and cascade filters is lacking in the literature. This dissertation tries to fill this gap.; By designing integrated {dollar}gsb{lcub}m{rcub}{dollar}-C filters based on the IFLF topology, four important problems are addressed that have not been dealt with comprehensively in the literature; solutions are given in this thesis. One: The design of integrated filters based on multiple-loop feedback topologies. Two: The comparison of sensitivity performances between continuous-time integrated IFLF cascade topologies, both using the {dollar}gsb{lcub}m{rcub}{dollar}-C technique. Three: The design of tuning methods for integrated continuous-time filters. Four: Measurement and simulation of integrated high-frequency fully-differential operational transconductance amplifiers (OTAs) and filters.; The complete design procedures of integrated CMOS {dollar}gsb{lcub}m{rcub}{dollar}-C filters by using the IFLF topology as a vehicle are presented in detail. The results of this research provide a good reference point to industry about the possible risk in realizing multiple-loop feedback filters in general, and the IFLF topology in particular. Complete design method, including transfer function design, OTA design, practical sensitivity analysis and simulations, lay-out techniques, tuning circuit design, test board design, and measurement techniques of integrated high-frequency fully-differential analog circuits, are presented. They can be used as guidelines for practical high-frequency continuous-time filter design.
机译:本文的主题是一种新的设计方法,用于集成{dollar} gsb {lcub} m {rcub} {dollar} -C滤波器,即领导者逆反馈(IFLF)拓扑。这种新方法是众所周知的多回路反馈拓扑之一。已知IFLF滤波器对分量变化的幅度敏感性要优于级联带通滤波器。对于现代应用,例如硬盘驱动器和无线通信,滤波器的群延迟很重要。但是,文献中缺少有关IFLF和级联滤波器之间的群时延性能的比较信息。本文试图弥补这一空白。通过基于IFLF拓扑设计集成的{gsb} gsb {lcub} m {rcub} {dollar} -C滤波器,解决了四个尚未在文献中全面解决的重要问题。本文给出了解决方案。一:基于多回路反馈拓扑的集成滤波器设计。第二:使用{dollar} gsb {lcub} m {rcub} {dollar} -C技术比较连续时间集成IFLF级联拓扑之间的灵敏度性能。第三:集成连续时间滤波器的调谐方法设计。四:集成高频全差分运算跨导放大器(OTA)和滤波器的测量和仿真。详细介绍了以IFLF拓扑为载体的集成CMOS gsb glcb lcm m rcub C滤波器的完整设计过程。这项研究的结果为工业界提供了一个很好的参考点,说明了在总体上实现多回路反馈滤波器(尤其是IFLF拓扑)可能存在的风险。提出了完整的设计方法,包括传递函数设计,OTA设计,实用的灵敏度分析和仿真,布局技术,调谐电路设计,测试板设计以及集成的高频全差分模拟电路的测量技术。它们可以用作实际高频连续时间滤波器设计的准则。

著录项

  • 作者

    Chiang, David Hsiu-Chun.;

  • 作者单位

    Portland State University.;

  • 授予单位 Portland State University.;
  • 学科 Engineering Electronics and Electrical.
  • 学位 Ph.D.
  • 年度 1998
  • 页码 181 p.
  • 总页数 181
  • 原文格式 PDF
  • 正文语种 eng
  • 中图分类 无线电电子学、电信技术;
  • 关键词

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