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Schottky Barrier MOSFETs working in the linear regime: A Monte Carlo study of microscopic transport

机译:线性状态下的肖特基势垒MOSFET:微观传输的蒙特卡洛研究

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This paper presents a detailed study (using a 2D Monte Carlo simulator) of the impact on electronic transport of dopant segregation layers in Schottky Barrier MOSFETs operating under the linear regime. It is shown that with a careful control of the layer parameters the performance of the devices are significantly improved, with a boosting of the drive current and an important reduction of the linear resistance (Rds(on)). The origin of these advantages can be related to internal microscopic transport quantities like transit time, distance travelled, scattering mechanisms, etc. The enhanced performance of Schottky Barrier MOSFETs including dopant segregation layers confirms the suitability of this technology to help extending the IRTS roadmap for Silicon MOS devices.
机译:本文提供了一个详细的研究(使用2D蒙特卡罗仿真器)对在线性状态下工作的肖特基势垒MOSFET中的掺杂剂隔离层电子传输的影响。结果表明,通过仔细控制层参数,可以显着提高器件的性能,同时可以提高驱动电流并显着降低线性电阻(Rds(on))。这些优势的根源可能与内部微观传输量有关,例如渡越时间,行进距离,散射机制等。肖特基势垒MOSFET的增强性能(包括掺杂剂隔离层)证实了该技术的适用性,有助于扩展硅的IRTS路线图MOS器件。

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