Through researching the structural characteristics of LDPC parity matrix and algorithm data flow features of LDPC code, an improved type of algorithm decoder of LDPC code is designed in this paper. The decoder includes expandable storage array, exquisite address-controlling unit and powerful sequential state-controlling machine. It possesses the advantages of expanding the decoding code length flexibly and lower complexity for hardware realizing and higher hardware resource utilization rate. After constructing communication system and testing the performance of hardware decoder, the results showed that the performance of the decoder and the theory simulation value can fit each other perfectly. The correctness of the design is proved. The decoder which is designed in this paper can provide valuable reference for the development of general chips for LDPC decoder.
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