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Engaging Undergraduate Students in Nano-Scale Circuit Research using Summer Internship

机译:使用暑期实习,从事本科生在纳米级电路研究中

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Semiconductor technology has been scaling at a steady pace following Moore's law. The current generations of the technology have reached dimensions well below 100nm where nano-scale phenomena are prominent. Transistors in such a small scale behave very differently than the classic long channel devices taught in most undergraduate level textbooks. Moreover, there are new challenges in nano-scale circuit design, such as process variations and reliability issues that are not taught in undergraduate level courses. Working on latest technology issues is typically an opportunity available only to graduate level students working on related research projects. To address this gap, using a NASA Curriculum Improvements Partnership Award for the Integration of Research (CIPAIR) grant, we have created a summer internship program that engages community college students in research projects on the latest challenges of circuit design in nano-scale semiconductor technology. Through this program, four community college students were mentored by two graduate students in a research project to analyze performance degradation of integrated circuits due to transistor aging effects in nano-scale. In this research, analysis of transistor breakdown was performed through computer simulations to understand effects on circuit power and performance. A ring oscillator circuit was utilized as a generic logic circuit for this research. The breakdown was modeled by resistors placed between the transistor terminals. The value of the resistor represents the severity of the breakdown; large resistors represent fresh transistors, whereas low resistors represent a fully broken transistor. In addition to computer simulations, real ICs were studied by taking power measurements experimentally. This research aims to offer better insight into the impact of transistor breakdown and to improve IC design in nano-scale. Through this internship program, the undergraduate students not only contributed to research and discovery, but also gained valuable experience and knowledge of nano-scale circuits that could have not been achieved in traditional educational methods.
机译:半导体技术在摩尔定律之后的稳定上缩放。目前的技术几代人达到尺寸远低于100nm,其中纳米级现象是突出的。这种小规模中的晶体管的行为非常不同于大多数本科教科书中教授的经典长信程设备。此外,纳米级电路设计中存在新的挑战,例如在本科级别课程中没有教授的过程变化和可靠性问题。致力于最新的技术问题通常是仅适用于研究相关研究项目的研究生级别的机会。为了解决这一差距,使用美国宇航局课程改进伙伴关系融合(CIPAIR)GRANT,我们创建了一个暑期实习计划,从事纳米级半导体技术电路设计的最新挑战的社区大学生研究项目。通过这个计划,在研究项目中,四名社区大学生被两位研究生融合,以分析由于纳米级晶体管老化效应导致集成电路的性能下降。在该研究中,通过计算机模拟进行晶体管击穿的分析,以了解电路功率和性能的影响。环形振荡器电路用作本研究的通用逻辑电路。通过放置在晶体管端子之间的电阻器建模的击穿。电阻的值代表击穿的严重程度;大电阻器代表新鲜晶体管,而低电阻器代表完全断开的晶体管。除了计算机模拟之外,通过通过实验进行电力测量来研究实际IC。本研究旨在更好地介绍晶体管击穿的影响,并以纳米尺度改善IC设计。通过这个实习计划,本科生不仅有助于研究和发现,而且还获得了在传统教育方法中无法实现的纳米级电路的宝贵经验和知识。

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