Diebond process is one of the key assembly process step in terms of defining reliability and performance of an integrated circuit, IC product. The process requires epoxy dispense accuracy and consistency to ensure that IC is secured and within the required position in the lead frame pad ready for wire bonding. These requirements though in the realm of assembly manufacturing is easier said than done. In the actual manufacturing Diebond process environment, there are several machine technologies that process different devices of IC. This complex condition coupled with increasing volume for processing was observed to be potentially related to the increase of Epoxy bridging defect. Normally a unit of IC with Epoxy bridging defect fails electrical testing as the conductive epoxy tails or spreads connecting the lead frame flag and the internal leads causing electrical short. However there are cases of very thin Epoxy bridging that can pass electrical test which has a risk of failing during application. ON Semiconductor Philippines Inc, OSPI formed a DMAIC team to immediately address opportunities in the trend of Epoxy bridging. Using the disciplined Six Sigma approach, the team identified Z level offset and Z level position as key input variable, KPIV using a resolution 4 fractional factorial design of experiment. These KPIV was found necessary as standard for all Diebond machine technologies. And even with the complexity of number of devices, with this KPIV's controlled and locked, Epoxy bridging was eliminated.
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