A 10Gb/s SONET-Compliant CMOS Transceiver with Low Cross-Talk and Intrinsic Jitter

摘要

A single-chip full-rate transceiver in 0.13μm standard CMOS consumes less than 1W. By using a special power-supply concept and a notched high-Q inductor in the VCO, the IC achieves a 0.2ps rms jitter. A limiting amplifier with a sensitivity of 20mV at 7GHz BW enables the CDR to recover data with a BER of <10{sup}(-12).