A Novel Scan-based Yield Enhancement Methodology for Faster Yield Ramp

摘要

Scan chain integrity yield loss is a common concern, especially in early stage of product yield ramp. Typically, scan chain failure diagnosis can only proceed upon full silicon build and structural test. In this work, we propose a proactive methodology which enables failure debug step to be initiated as early as the onset of device fabrication, to bring forward yield learning. Scan chain cells and nets information are extracted from design data file and converted to inline optical wafer inspection care areas. In this way, the inspection recipe can be optimized for the detection of scan chain related defects. It is shown experimentally that such approach can potentially enhance general defect detection sensitivity by 50% and increase the defect hit probability on scan chain nets. Any findings serve as useful early data for process improvement feedback. Furthermore, marginal defects, which otherwise are not easily revealed using conventional approach, can also be detected to provide early warning for process drifts or variations.