Bufferless resonant clocking with low skew and high variation-tolerant

摘要

Bufferless resonant clock distribution network can minimize clock power consumption in synchronous system. But without buffers, the clock skew is subject to many factors, such as differential parasitic parameters in clock wires, imbalanced clock load and process-voltage-temperature (PVT) variations. In this paper, we propose a hierarchical interconnection network with two-phase bufferless resonant clock distribution, which mixes mesh and tree architecture together. The problems of skew reduction and variation-tolerance in the mixed interconnection network are studied through a pipelined multiplier under TSMC 65nm standard CMOS process. Post-simulation results show that, the hierarchical architecture reduces more than 75% clock skew compared with pure mesh network. The maximum skew in the proposed clock distribution is less than 7ps under PVT variations, which is no more than 1% of the clock cycle of about 760ps.