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A level shifter with logic error correction circuit for extremely low-voltage digital CMOS LSIs

机译:具有逻辑错误校正电路的电平转换器,用于极低压数字CMOS LSI

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A level shifter circuit capable of extremely low-voltage inputs is presented in this paper. The circuit has a distinctive feature in current generation scheme with logic error correction circuit by detecting input and output logic levels. The proposed circuit can convert low-voltage input digital signals into high-voltage output digital signals. The circuit achieves low-power operation because it dissipates operating current only when the input signals change. Measurement results demonstrated that the circuit can convert low-voltage input signals of 0.4 V into 3 V output signals. The power dissipation was 58 nW at 0.4-V and 10-kHz input pulse.
机译:本文提出了一种具有极低电压输入能力的电平转换器电路。该电路通过检测输入和输出逻辑电平,在具有逻辑错误校正电路的电流生成方案中具有鲜明的特征。所提出的电路可以将低压输入数字信号转换成高压输出数字信号。该电路仅在输入信号发生变化时才消耗工作电流,因此可实现低功耗工作。测量结果表明,该电路可以将0.4 V的低压输入信号转换为3 V的输出信号。在0.4V和10kHz输入脉冲下的功耗为58nW。

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