KERFLESS WAFERING APPROACH WITH SI AND GE TEMPLATES FOR SI, GE AND Ill-V EPITAXY

摘要

We work on the transfer from CZ wafers to epitaxially grown Si and Ge wafers on reusable substrates with a porous detachment layer ("kerfless wafering") to reduce material and energy consumption. We report on our progress of applying the kerfless wafering approach to Si and to Ge wafers. For Si, we develop templates and epitaxially grown wafers (SiEpiWafers) since many years in our self-made CVD reactor ("RTCVD") and are now bringing their quality to the next level with a new, microelectronic CVD reactor ("PEpi") which allows us to grow 6" and 156×156 mm~2 (MO) epitaxial Si wafers with adjustable thickness and doping level (n- and p-type). In the first test runs, we achieved as-grown lifetimes up to 840 μs and a total thickness variation of ～ 10%. For Ge, we were successful in developing and understanding a porous layer stack leading to 4" detachable Ge templates for future Ge or III-V epitaxial growth.