Design of digitally assisted 1.5b/stage pipeline ADCs using fully differential current conveyors

摘要

This paper introduces 1.5b/stage pipeline ADCs based on a fully differential current conveyor (CC). A comparison between the traditional MDAC architecture and the passive common mode suppressed MDAC as well as a new foreground calibration technique to correct the ADC errors is presented. The ADCs implemented in 90nm work at 10MHz sampling rate for input voltages of (−500mV, 500mV) and provide varying resolutions of 8 and 10 bits.