MULTI-STAGE SUCCESSIVE APPROXIMATION REGISTER ANALOG TO DIGITAL CONVERTER, CAPABLE OF MAINTAINING A WORKING SPEED WHICH IS SIMILAR TO THE SPEED OF A PIPELINE ADC, AND ANALOG TO DIGITAL CONVERSION METHOD THEREOF

摘要

PURPOSE: A multi-stage successive approximation register analog to digital converter and an analog to digital conversion method thereof are provided to reduce analog to digital conversion time by improving an analog to digital conversion method.;CONSTITUTION: A first SAR(Successive Approximation Register) ADC(300) changes a first analog input voltage to a n-bit digital. A second SAR ADC(310) changes the residual voltage of the first SAR ADC to a m-bit digital. The first SAR ADC changes the second analog input voltage to a digital during the residual voltage digital conversion period of the second SAR ADC.;COPYRIGHT KIPO 2010