PN-Assisted Deterministic Digital Background Calibration of Multistage Split-Pipelined ADC

摘要

A digital background calibration technique to treat capacitor mismatch, residue gain error, and nonlinearity in a pipelined ADC based on the split-ADC architecture is reported. Although multiple works have been reported before on the split- calibration of pipelined ADCs, none of them is comprehensive, i.e., capacitor mismatch, residue gain error, and nonlinearity are never treated in one work at the same time. We, also for the first time, recognize the multistage pipelined ADC with residue nonlinearity calibration as a Nonlinear Least Squares problem. Behavioral simulation results demonstrate the efficacy of the technique, in which the SNDR and SFDR performance of a 15-bit split-pipelined ADC are improved from 42 dB and 50 dB to 88 dB and 102 dB on average, respectively.