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Characterizing Memory Write References for Efficient Management of Hybrid PCM and DRAM Memory

机译:表征存储器写入参考,可有效管理混合PCM和DRAM存储器

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In order to reduce the energy dissipation in main memory of computer systems, phase change memory (PCM) has emerged as one of the most promising technologies to incorporate into the memory hierarchy. However, PCM has two critical weaknesses to substitute DRAM memory in its entirety. First, the number of write operations allowed to each PCM cell is limited. Second, write access time of PCM is about 6-10 times slower than that of DRAM. To cope with this situation, hybrid memory architectures that use a small amount of DRAM together with PCM memory have been suggested. In this paper, we present a new memory management technique for hybrid PCM and DRAM memory architecture that efficiently hides the slow write performance of PCM. Specifically, we aim to estimate future write references accurately and then absorb most memory writes into DRAM. To do this, we analyze the characteristics of memory write references and find two noticeable phenomena. First, using write history alone performs better than using both read and write history in estimating future write references. Second, the frequency characteristic is a better estimator than temporal locality but combining these two properties appropriately leads to even better results. Based on these two observations, we present a new page replacement algorithm called CLOCK-DWF (CLOCK with Dirty bits and Write Frequency) that significantly reduces the number of write operations that occur on PCM.
机译:为了减少计算机系统主存储器中的能量消耗,相变存储器(PCM)已经成为整合到存储器层次结构中最有前途的技术之一。但是,PCM有两个严重的弱点,无法整体上替代DRAM存储器。首先,限制了对每个PCM单元的写入操作的数量。其次,PCM的写访问时间比DRAM慢6到10倍。为了应对这种情况,已经提出了使用少量DRAM和PCM存储器的混合存储器架构。在本文中,我们提出了一种用于混合PCM和DRAM存储器体系结构的新存储器管理技术,该技术有效地掩盖了PCM的慢写入性能。具体来说,我们的目标是准确估计未来的写入参考,然后将大多数内存写入DRAM中。为此,我们分析了内存写引用的特征,并发现了两个值得注意的现象。首先,在估计将来的写引用时,单独使用写历史记录要比同时使用读和写历史记录更好。其次,频率特性比时间局部性是更好的估计器,但是适当地组合这两个特性可以得到更好的结果。基于这两个发现,我们提出了一种称为CLOCK-DWF(带有脏位和写入频率的CLOCK)的新页面替换算法,该算法可以大大减少PCM上发生的写入操作的次数。

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