A new power aware bus encoding scheme for system on a chip

摘要

In ultra-deep submicron technology, minimizing the propagation delay and power consumption on buses is two of the most important design objectives in system-on-chip (SOC) design. Crosstalk between adjacent wires on the bus may create a significant portion of propagation delay. Elimination or minimization of such faults is crucial to the performance and reliability of SOC designs. In this paper, we propose a new bus encoding scheme which is capable to eliminate effectively crosstalk problems in bus partitions as well as inter-partitions using shielding wires. The experiment shows that the proposed coding technique can save the dynamic power up to 63% for 24 bit buses, while totally avoiding the crosstalk delay.