In this paper, we present a power macromodeling technique for transistor level. The proposed technique is used to estimate the power dissipation on conventional metal-oxide-semiconductor (MOS) transistors. As the dynamic power is directly linked with the load capacitance (CL), it is also a lumped capacitance of all internal parasitic capacitances. In our model, we take an account of the parasitic capacitances with their dependence on channel width and the length. Suitable values of other factors (i.e. threshold voltage VT, gate voltage VGS, drain voltage VDD etc.) are used for the power consumption of the MOS transistors. The Preliminary results are effective and our macromodel provides the accurate power estimation.
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机译：在本文中，我们提出了一种用于晶体管级的功率宏建模技术。所提出的技术用于估计常规金属氧化物半导体（MOS）晶体管上的功耗。由于动态功率与负载电容（C L ）直接相关，因此它也是所有内部寄生电容的集总电容。在我们的模型中，我们考虑了寄生电容及其对通道宽度和长度的依赖性。其他因素的合适值（例如，阈值电压V T ，栅极电压V GS ，漏极电压V DD 等）用于功率MOS晶体管的消耗。初步结果是有效的，我们的宏模型提供了准确的功率估算。
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