Modified reduced delay BCD adder

摘要

Current trends in the academia and industry is managing and processing a high volume of data. Most of the time is spend on converting the data from decimal to binary, processing and converting back to decimal. The direct production of decimal sum offers a significant improvement in addition over methods requiring decimal correction. Here is the proposition which will reduce the conversion and processing time. This work is the extension of Alp Arslan Bayracci and Ahmet Akkas et al of reduced delay Binary Coded Decimal (BCD) adder. In some corner case, adder design was misbehaving and has been corrected and presented.