The increasing complexity of analog design for SoCs has become a bottleneck due to the lack of established design automation flows. Consequently, reuse of analog design IP (intellectual property) is becoming increasingly prevalent in the semiconductor industry. Traditional design reuse approaches still require a considerable amount of a designer's time for a new set of specifications or migration to new technology nodes. This paper describes an accelerated design reuse strategy for analog circuit design using design automation techniques. As a case study, we developed an automated GmC filter design flow using a combination of heuristic and stochastic optimization methods. The resultant IP is capable of generating SPICE netlists for wide sets of specifications and different technology nodes with minimal designer effort.
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机译：由于缺乏已建立的设计自动化流程，用于SoC的模拟设计的日益复杂性已成为瓶颈。因此，在半导体行业中，模拟设计IP（知识产权）的重用变得越来越普遍。传统的设计重用方法仍然需要大量的设计者时间来使用一组新的规范或迁移到新技术节点。本文介绍了使用设计自动化技术进行模拟电路设计的加速设计重用策略。作为案例研究，我们结合了启发式和随机优化方法，开发了自动的G m C滤波器设计流程。由此产生的IP能够以最少的设计人员工作来生成适用于各种规格和不同技术节点的SPICE网表。
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