A 1.7Gbps DLL-based Clock Data Recovery in 0.35µm CMOS

摘要

This paper presents a DLL(Delay Locked Loop)-based CDR(Clock Data Recovery) design with nB(n+2)B data formatting scheme. Due to the proposed data formatting scheme, the CDR does not require the external reference clock. The proposed nB(n+2)B data formatting scheme is done by inserting the ‘01’ pattern in every N-bit data. To prove the feasibility of the scheme, a 1.7Gbps CDR is designed, simulated and fabricated. The proposed CDR achieves less jitter due to the DLL structure. The proposed 1.7Gbps CDR with the 10B12B data formatting consumes approximately 8mA under 3.3V power supply using 0.35µm CMOS process.