2.488 Gbit/s clock and data recovery circuit in 0.35 mum CMOS

摘要

The design of a 2.488 Gbit/s clock and data recovery (CDR) IC for synchronous digital hierarchy (SDH) STM-16 receiver is described. Based on the injected phase-locked loop (IPLL) and D-flip flop architectures, the CDR IC was implemented in a standard 0. 35 mum complementary metal-oxide-semiconductor (CMOS) technology. With 2~(31) -1 pseudorandom bit sequences (PRBS) input, the sensitivity of data recovery circuit is less than 20 mV with 10~(-12) bit error rate (BER). The recovered clock shows a root mean square (rms) jitter of 2. 8 ps and a phase noise of -110 dBc/Hz at 100 kHz offset. The capture range of the circuit is larger than 40 MHz. With a 5 V supply, the circuit consumes 680 mW and the chip area is 1. 49 mm X 1 mm.