To ensure that an intellectual property (IP) block is validated ahead of its use in an ‘unknown’ system-on-chip (SoC) context, an holistic view of the integration process must be taken. We will focus on the challenges faced in integrating and manufacturing advanced low-power processor based SoC systems, which have dramatically increased the complexity & state space for logical and electrical validation. We describe the process taken by IP providers, tool vendors and the foundry supply chain to enable first time logical, electrical and manufacturing closure. We discuss how feedback is used to improve component IP validation strategies and interoperability and integration testing. We also cover techniques such as the role of hardware/software emulation for configuration testing, the application of formal techniques and advanced electrical rules checking. In addition, we will examine the role waivers and automated design-in guidelines to enable the integrator to balance risk reduction and design turnaround time. Finally we discuss manufacturing tests and how to link these back to improve the metrics used for component and integration level testing.
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