Optimization of Switching Metrics for CMOS Integrated HfO2 based RRAM Devices on 300 mm Wafer Platform

摘要

In this work, we improved switching reliability with respect to memory window, switching variability and switching yield of 65nm CMOS integrated hafnium oxide (HfO2) based RRAM devices by SET/RESET process optimization. Switching performance of 1 transistor 1 RRAM (1T1R) cells as a function of operating current, SET/RESET pulse width and amplitude were investigated in depth, and full 300mm wafer scale switching optimization for the devices was demonstrated. The devices were also optimized for long cycling endurance (up to 10^{9 cycles) and retention behavior at 373 K.}