A 3-dimensional Vernier ring time-to-digital converter in 0.13µm CMOS

摘要

A 3-dimensional Vernier ring time-to-digital converter (TDC) is presented for the first time that greatly improves the measurement time and power consumption and achieves large detectable range and fine resolution simultaneously. The TDC prototype chip achieves 16.5-ps resolution and an 8-bit detectable range with 0.16 mm² die area in a 0.13µm CMOS technology. The power consumption for the entire TDC is only 4.5mW with 1.5V power supply at 15MSps sample rate.