The design of a 0.18-ÃÂÿm CMOS digital control architecture for a buck converter is presented. Several features are implemented. These include: 1) Frequency-domain digitization technique based on first-order non-feedback Sigma-Delta frequency Discriminators (NF-SDFD); 2) a robust arrangement for the feedback ADCs to guard against false output voltage variation due to temperature and process variation; 3) A new improved hybrid Digital Pulse Width Modulator (DPWM) architecture. The proposed system has additional attractive futures such simplicity, scalability, low power, close to all digital implementation in addition to its capability of satisfying tight regulation requirements for wide range of applications. An 8-bit ADC resolution is achieved with less than 110 ÃÂÿA current consumption. A 9-bit DPWM consumes around 370 ÃÂÿA. A 2% output voltage regulation accuracy is achieved with less than 10 mVpp ripple.
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