基于 WSAR-ADC的降压型 DC-DC 控制器设计

摘要

设计了一种基于加窗逐次逼近寄存器（ WSAR）模拟数字转换器（ ADC）的降压型DC-DC控制器，这种WSAR-ADC适用于数字电源系统，通过对输入电压进行加窗处理，能有效地降低芯片的复杂度；并利用蚁群算法，对该DC-DC控制器的比例积分微分（PID）参数进行了整定，使得整个系统能够稳定工作。电路使用BCD（Bipolar/CMOS/DMOS）0．5μm工艺，输入电压3．3 V，输出电压1 V，设计最大负载电流2 A，纹波小于9 mV，开关频率500 kHz。经过验证，该降压型DC-DC控制器能满足数字电源的采样需求。%A buck DC-DC controller based on window successive approximation register ( WSAR) and analog-to-digital converter ( ADC) was designed.It is applicable to digital power system.The circuit complexity can be re-duced by adding the window function to process input voltage;and the PID (proportion integration differentiation) parameters setting of the DC-DC controller is completed using the ant colony algorithm, which makes the whole sys-tem work stably.The circuit is implemented under Bipolar/CMOS/DMOS ( BCD) 0.5μm process, the input volt-age is 3.3 V, and the output voltage is 1 V.The designed maximum load current is 2 A, the ripple of output voltage is less than 9 mV.After verification, the switch frequency is 500 kHz.This buck DC-DC controller can meet the demand of digital power sampling.