Clock buffer polarity assignment considering the effect of delay variations

摘要

This work addresses the problem of minimizing power/ground noise with an important design parameter, which is the delay variations on the clock tree. Without considering the effect of delay variations on the polarity assignment, the resulting statistical clock skew may lead to a high probability of skew violation, which causes a low yield of design. Given distributions on the delay of each type of buffering elements and the interconnect delay from the clock source to every flip-flop with spatial delay correlations, and the clock skew and yield constraints, we solve the problem of assigning polarity to each sink buffer (i.e., assigning a buffering type) so that the power/ground noise is minimized while satisfying the yield and clock skew constraints. Specifically, we solve the problem in two steps where in step 1, for each pair of sinks a set of feasible combination(s) of polarities to the sinks that do not violate the yield constraint as well as the clock skew constraint is extracted, and in step 2, a stepwise greedy method is applied to determine the polarities to sinks from the feasible sets obtained in step 1 to minimize the power/ground noise. Through experiments with ISCAS89 benchmark circuits, it is shown that our proposed approach is able to improve yield by 6.7% on average even with 4.3% less power and 4.4% less ground noises over the results by the conventional polarity assignment approach which does not consider the delay variations.