Layout-aware multi-cell upsets effects analysis on TMR circuits implemented on SRAM-based FPGAs

机译：对基于SRAM的FPGA上实现的TMR电路具有布局意识的多单元扰动效果分析

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摘要

We developed a tool combining the layout information obtained from laser screening of a device with an algorithm for estimating multi-cell upsets effects on TMR circuits implemented on SRAM-based FPGAs. Detailed experimental results are provided.

机译：我们开发了一种工具，该工具将通过对设备进行激光筛选获得的布局信息与一种算法相结合，以估算在基于SRAM的FPGA上实现的TMR电路上的多单元扰动效应。提供了详细的实验结果。

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《2009 European Conference on Radiation and Its Effects on Components and Systems》|2009年|p.98-101|共4页
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Sterpone L.; Violante M.; Bocquillon A.; Miller F.; Buard N.; Manuzzato A.; Gerardin S.; Pacagnella A.;
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中图分类无线电技术;
关键词
Laser testing; Multi-Cell Upsets; SRAM-based FPGAs; Static Analysis;

机译：激光测试;多单元干扰;基于SRAM的FPGA;静态分析;

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专利

1. Layout-Aware Multi-Cell Upsets Effects Analysis on TMR Circuits Implemented on SRAM-Based FPGAs [J] . Sterpone L., Violante M., Panariti A., Nuclear Science, IEEE Transactions on . 2011,第5期

机译：在基于SRAM的FPGA上实现的TMR电路的布局感知多单元扰动效应分析
2. A new analytical approach to estimate the effects of SEUs in TMR architectures implemented through SRAM-based FPGAs [J] . Sterpone L., Violante M. IEEE Transactions on Nuclear Science . 2005,第6期

机译：一种新的分析方法，用于评估SEU在通过基于SRAM的FPGA实现的TMR架构中的影响
3. A New Algorithm for the Analysis of the MCUs Sensitiveness of TMR Architectures in SRAM-Based FPGAs [J] . Sterpone L., Violante M. IEEE Transactions on Nuclear Science . 2008,第4期

机译：基于SRAM的FPGA中TMR架构的MCU敏感性分析的新算法
4. Layout-aware multi-cell upsets effects analysis on TMR circuits implemented on SRAM-based FPGAs [C] . Sterpone L., Violante M., Bocquillon A., European Conference on Radiation and its Effects on Components and Systems . 2009

机译：基于SRAM的FPGA实现的TMR电路的布局感知多单元upsets效应分析
5. Hardware and Software Fault-Tolerance of Softcore Processors Implemented in SRAM-Based FPGAs [D] . Rollins, Nathaniel H. 2012

机译：基于SRAM的FPGA中实现的软核处理器的硬件和软件容错
6. A Method of FPGA-Based Extraction of High-Precision Time-Difference Information and Implementation of Its Hardware Circuit [O] . Jian Li, Xinlei Yan, Maojin Li, 2019

机译：基于FPGA的高精度时差信息提取方法及其硬件电路的实现
7. Analysis and Test of the Effects of Single Event Upsets Affecting the Configuration Memory of SRAM-based FPGAs [O] . CASSANO, LUCA MARIA 2013

机译：分析和测试单个事件扰动对基于SRAM的FPGA配置存储器的影响

Layout-aware multi-cell upsets effects analysis on TMR circuits implemented on SRAM-based FPGAs

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