2-Metal-layer interposer for high-speed devices

摘要

As both device pin density and system frequency increase, printed circuit board layout becomes more complex. A successful high-speed printed circuit board design must effectively integrate the devices and other elements, while avoiding signal transmission problems that are associated with high-speed IO standards. This is evident in the memory platform where the data rate is reaching the GHz zone. Stringent designs like matched IO traces and effective ground/power metal plane are required to ensure signal integrity. Existing DRAM packages are supported by a 1-metal-layer interposer in a BOC (Board on Chip) package. However, demand for higher speed performance and an industrial push for low- power efficient devices (data server market), there is a need to look at the packaging requirements.