A new concept and CMOS implementation of an analog current-mode memory with increased retention time is presented. Because the memory is of a capacitive type, there are difficulties with long-term storing the written information, when its basic form is used [3]–[4]. To overcome this problem, we propose applying a positive feedback which ensures obtaining the same base potential of the memory sample & hold switch as the potential across the holding capacitor. As a result, holding time of the memory has been increased by several orders of magnitude compared to that of the basic memory with no enlargement in the memory writing time. Simulation results are shown to be in a good agreement with theoretic considerations. The proposed memory cell can operate with a low power losses when properly designed. An influence of transistor size mismatching, characteristic for analog circuits, on the memory properties is also discussed and, although visible, appears not to be critical.
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