Simple and easy-to-use formulas have been obtained for the evaluation of the elastic stability of flat-and-large-diameter copper vias fabricated in silicon wafers and subjected, at elevated temperature conditions, to thermally induced compression because of the thermal expansion mismatch of the copper and the silicon materials. A simple and practically useful calculation procedure has been developed for the evaluation of the effect of the combined action of several adjacent vias on the state-of-stress at the given point of the silicon wafer. Based on the carried out computations, it has been concluded that the maximum tensile stress in the silicon wafer could be assessed by multiplying the computed "hoop" pressure by the factor of 2.25.
展开▼
