INFLUENCE OF WORST CASE CROSSTALK DUE TO MULTIPLE AGGRESSORS ON SINGLE VICTIM IN DSM CHIPS

摘要

In this paper the influence of crosstalk on single victim due to multiple aggressors in the same metal layer is studied. We develop here a crosstalk fault model based on the consideration of usual distributed coupling capacitance and RLGC parasitics of interconnects in addition to mutual conductance (resistive bridging) in order to deal the crosstalk influence. Here, we estimate the crosstalk influence for worst case input signal combinations on aggressors, which induce more crosstalk on single victim. Our model helps the System-on-Chip (SoC) designers by providing sufficient insights into Signal Integrity problems. Experimental simulations with our crosstalk model, carried out using Philips CMOS 12 (130nm) technology parameters, further validated with PSPICE simulations reveal that coupling capacitance's effect is more on crosstalk glitch and signal delay on victim's output whereas, the mutual conductance affects more on the final steady state value of the victim's output signal.