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INTEGRATED MODELING OF NANOTOPOGRAPHY IMPACT IN PATTERNED STI CMP

机译:图案CMP中纳米照相术的集成建模。

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As advancing technologies increase the demand for planarity in integrated circuits, nanotopography has emerged as an important concern in shallow trench isolation (STI) on wafers polished by means of chemical-mechanical planarization (CMP). Nanotopography ― starting silicon surface height variations 100 nm in amplitude extending across millimeter-scale lateral distances ― can result in CMP-induced localized thinning of surface films such as the oxides or nitride used in STI. In previous work, a two-step analysis of the effect of nanotopography on CMP has been reported. First, a contact wear model is used on a blanket wafer to understand how the underlying nanotopography impacts the time to clear oxide over nitride during CMP. Second, the additional dishing and erosion in patterned STI wafers due to the additional nanotopography-induced clearing time are simulated using a pattern-dependent STI CMP model. In this paper, we present two alternative approaches for simultaneous simulation of both pattern and nanotopography effects to better understand the impact of nanotopography on STI CMP. In the first approach, we perform a "pure" contact wear simulation on a finely discretized grid. Because of high computational demands, this approach is only feasible for one dimensional cut lines. In the second approach proposed here, an integrated model incorporating contact wear and density/step-height effects in STI CMP is used. A contact wear component accounts for pressure differentials across the chip due to long-range nanotopography and other surface height variations. Patterned feature effects are captured by a pattern density and step-height dependent component. This makes feasible 2D simulations of patterned structures over underlying uneven surfaces to study the effect of realistic nanotopography maps on the CMP of STI patterns. The simulation shows that nanotopography results in longer oxide clearing time, in agreement with previous work. Depending on the specific random configuration of any given nanotopography map, either more or less nitride erosion may result despite the increased polishing time. Thus nanotopography effects should be considered an additional component of STI nitride loss budgets, in addition to that required by layout pattern dependencies.
机译:随着先进技术的发展,对集成电路平面性的要求日益提高,纳米形貌已成为通过化学机械平面化(CMP)抛光的晶圆上浅沟槽隔离(STI)的重要关注点。纳米形貌-硅表面高度的变化幅度跨越毫米尺度的横向距离开始100 nm-会导致CMP引起的表面膜(例如STI中使用的氧化物或氮化物)的局部变薄。在以前的工作中,已经报道了纳米形貌对CMP的影响的两步分析。首先,在毯式晶圆上使用接触磨损模型来了解底层的纳米形貌如何影响CMP过程中氮化物上清除氧化物的时间。其次,使用依赖于图案的STI CMP模型模拟了由于额外的纳米形貌诱导的清除时间而导致的图案化STI晶片中的额外凹陷和腐蚀。在本文中,我们提出了两种同时模拟图案和纳米形貌效应的替代方法,以更好地了解纳米形貌对STI CMP的影响。在第一种方法中,我们在精细离散的网格上执行“纯”接触磨损模拟。由于较高的计算需求,此方法仅对一维切割线可行。在这里提出的第二种方法中,使用了在STI CMP中结合了接触磨损和密度/台阶高度效应的集成模型。接触磨损组件说明了由于长距离纳米形貌和其他表面高度变化而导致的芯片两端的压差。图案化特征效果由图案密度和步高相关组件捕获。这使得在下面的不平坦表面上的图案化结构的2D模拟成为可能,以研究现实的纳米形貌图对STI图案CMP的影响。模拟表明,纳米形貌导致更长的氧化物清除时间,这与以前的工作相符。取决于任何给定纳米形貌图的特定随机配置,尽管抛光时间增加了,但还是会导致或多或少的氮化物腐蚀。因此,除了布局图案依赖性之外,纳米形貌效应还应被视为STI氮化物损耗预算的额外组成部分。

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