Analysis and minimization techniques for total leakage considering gate oxide leakage

摘要

In this paper we address the growing issue of gate oxide leakage current (Igate) at the circuit level. Specifically, we develop a fast approach to analyze the total leakage power of a large circuit block, considering both Igate and subthreshold leakage (Isub). The interaction between Isub and Igate complicates analysis in arbitrary CMOS topologies and we propose simple and accurate heuristics based on table look-ups to quickly estimate the state-dependent total leakage current within 1% of SPICE. We then make several observations on the impact of Igate in designs that are standby power limited, including the role of device ordering within a stack and the differing state dependencies for NOR vs. NAND topologies. Based on these observations, we propose the use of pin reordering as a means to reduce Igate due to the dependence of gate leakage on stack node voltages.