Implementing Listless Minimum Zerotree Coding with FPGA

摘要

A Listless Minimum Zerotree Coding algorithm (LMZC) on Field Programmable Gate Array (FPGA) is proposed to adopt a minimum zerotree of wavelet coefficients and a listless significance map coding with a new scanning order and new flag maps different from Listless Zerotree Coding (LZC) to reduce the memory requirement and increase the compression performance. Additionally, a pipelined hardware architecture is utilized, and characterized with higher speed and higher compression performance. Simulation results show that this scheme is feasible.