This paper proposes a novel VLSI architecture for an FIR filter chip providing variable-length taps. To change the number of taps, we propose two special features called a data-reuse structure and a recurrent-coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a module unit. Since parallel multipliers occupy a large VLSI area, a filter chip using bit-serial multipliers meeting the real-time requirement specification can dramatically save the area. We propose a modified bit-serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter can be twice faster than previous filters using bit-serial multipliers. We developed VHDL models and performed logic synthesis using the SYNOPSYS/sup TM/ CAD tool with the 0.8 /spl mu/m SOG cell library (HSG30042). The chip has only 9,507 gates, was fabricated, and is running at 77 MHz.
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机译：本文提出了一种用于提供可变长度抽头的FIR滤波器芯片的新型VLSI架构。要更改抽头数，我们提出了两个称为数据重用结构的特殊功能和复制系数方案。与使用地址生成单元和模块单元的现有芯片相比，这些功能包括几种Muxs和寄存器，并减少20％以上的栅极数量超过20％。由于并行乘法器占用大型VLSI区域，因此使用会满足实时需求规范的位串行乘法器的滤波器芯片可以显着保存该区域。我们提出了一种修改的比特串行乘法算法来平行计算两个部分产品，因此，所提出的滤波器可以使用比特串行乘法器的先前滤波器快两倍。我们开发了VHDL模型，并使用0.8 / SPL MU / M SOG单元库（HSG30042）的Synopsys / Sup TM / CAD工具进行了逻辑合成。该芯片仅制造了9,507个门，并在77 MHz处运行。
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