The paper proposes a novel VLSI architecture for a multiplierless FIR filter chip providing variable length taps. To change the number of taps, we propose two special features called a data reuse structure and a recurrent coefficient scheme. These features consist of several MUXs and registers and reduce the number of gates over 20% compared with existing chips using an address generation unit and a module unit. Since multipliers occupy a large VLSI area, a multiplierless filter chip meeting real time requirement can save a large area. We propose a modified bit serial multiplication algorithm to compute two partial products in parallel, and thus, the proposed filter is twice as fast and has smaller hardware than previous multiplierless filters. We developed Verilog HDL models and performed logic synthesis using the CADENCE/sup TM/ CAD tool with the Hyundai/sup TM/ 0.8 /spl mu/m SOG (sea-of-gate) cell library. The chip has only 9507 gates, was fabricated, and is running at 77 MHz.
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机译：本文提出了一种新颖的VLSI架构，用于提供可变长度抽头的无乘法器FIR滤波器芯片。为了改变抽头的数量，我们提出了两个特殊的功能，称为数据重用结构和递归系数方案。这些功能由多个MUX和寄存器组成，与使用地址生成单元和模块单元的现有芯片相比，其门数减少了20％以上。由于乘法器占用很大的VLSI面积，因此满足实时要求的无乘法器滤波器芯片可以节省很大的面积。我们提出了一种改进的比特串行乘法算法来并行计算两个部分乘积，因此，与以前的无乘法器滤波器相比，所提出的滤波器具有两倍的速度并且硬件更小。我们开发了Verilog HDL模型，并使用CADENCE / sup TM / CAD工具和现代/ sup TM / 0.8 / spl mu / m SOG（门海）单元库进行了逻辑综合。该芯片仅具有9507个门，已制成，并以77 MHz的速度运行。
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