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Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model

机译：高阶AWE模型下VLSI互连的同时缓冲区插入和非Hanan优化

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《International symposium on Physical design 》|1999年|P.133-138|共6页
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Jiang Hu; Sachin S. Sapatnekar;
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中图分类半导体技术 ;
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专利

1. Algorithms for non-Hanan-based optimization for VLSI interconnect under a higher-order AWE model [J] . Jiang Hu, Sapatnekar S.S. IEEE Transactions on Computer-Aided Design of Integrated Circuits and Systems . 2000 ,第4期

机译：高阶AWE模型下基于VLSI互连的非基于Hanan的优化算法
2. An improved RC model for VLSI interconnects with applications to buffer insertion [J] . Alaa R. Al-Taee, Fei Yuan, Andy Ye Analog Integrated Circuits and Signal Processing . 2014 ,第1期

机译：用于VLSI的改进的RC模型与用于缓冲区插入的应用程序互连
3. An Alternate Approach to Buffer Insertion for Delay and Power Reduction in VLSI Interconnects [J] . Sandeep Saini, A. Mahesh Kumar, Sreehari Veeramachaneni, Journal of Low Power Electronics . 2010 ,第3期

机译：VLSI互连中用于延迟和降低功耗的备用缓冲区插入方法
4. Simultaneous Routing and Buffer Insertion Algorithm for Interconnect Delay Optimization in VLSI Layout Design [C] . Mohamed Khalil Hani, Nasir Shaikh-Husin International Conference on Microelectronics . 2008

机译：VLSI布局设计中互连延迟优化的同时路由和缓冲插入算法
5. Modeling and optimization of VLSI interconnects. [D] . He, Lei. 1999

机译：VLSI互连的建模和优化。
6. Modeling the Insertion Mechanics of Flexible Neural Probes Coated with Sacrificial Polymers for Optimizing Probe Design [O] . Sagar Singh, Meng-Chen Lo, Vinod B. Damodaran, 2016

机译：建模牺牲性聚合物涂层的柔性神经探针的插入力学以优化探针设计
7. Simultaneous buffer insertion and nonhanan optimization for VLSI interconnect under a higher order AWE model [O] . Jiang Hu, Sachin S. Sapatnekar 1999

机译：高阶AWE模型下VLSI互连的同时缓冲区插入和nonhanan优化

Simultaneous buffer insertion and non-Hanan optimization for VLSI interconnect under a higher order AWE model

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