Technology Mapping for Delay-Minimization in LUT-based FPGA Designs

摘要

This paper presents a delay optimized technology mapping algorithm for LUT-based FPGA. The algorithm consists of a minimum delay mapping procedure under arbitrary net-delay model, a mapping-driven decomposition procedure for short delay, a post-processing procedure reducing the number of LUTs and a timing-driven placement procedure. It cna be proofed that the mapping procedure can obtain a minimum delay mapped circuit.